Field of the Invention
The invention relates to a semiconductor memory having a memory cell array and a multiplicity of word and bit lines and memory cells connected to the word and bit lines. The word lines can be driven by an active and a nonactive level. A control device is provided in order to cause the outputting of the nonactive level to the word lines.
Random access semiconductor memories, in particular having dynamic memory cells, so-called DRAMS (Dynamic Random Access Memories), have word lines and bit lines with memory cells arranged at their crossover points. A dynamic memory cell comprises a storage capacitor and a selection transistor. The control terminal of the selection transistor is connected to the word line. The controlled path of the selection transistor is connected to the storage capacitor at one end and to the bit line at the other end.
In the event of an access to a memory cell, for example a read access, the word line is activated by the application of an active level, so that the transistor is turned on. The storage capacitor is thereby connected to the bit line and outputs its charge onto the bit line. A sense amplifier subsequently amplifies the signal output from the storage capacitor to the bit line to form a full-level signal. The signal amplified by the sense amplifier is subsequently forwarded along the read-out data signal path as far as an output terminal, in order to be ready at the output of the semiconductor memory.
The charge content of the capacitor decreases on account of leakage currents. Therefore, the charge content in dynamic memories must be refreshed at predetermined time intervals. For this purpose, the signal amplified by the sense amplifier is written back to the memory cell via the open selection transistor. Both during the read-out and during the refresh, the word lines are activated and the amplifying operation at the sense amplifier is to be carried out until there is sufficient certainty that the read-out data value is present with a sufficiently stable level at the sense amplifier. Afterward, the activated word line can be deactivated again. In this case, a nonactive level, for example reference-ground potential or ground or even a negative level value, is output onto the word line. By contrast, the active level has a positive potential which is generated by means of voltage pumps in a manner even lying above the supply voltage fed in externally, in order that the selection transistor is completely turned on. In addition, the bit lines are precharged to an equalization level. This deactivation operation is referred to as precharge.
The correctly timed application of the nonactive level to previously selected word lines is important. If the word lines are turned off too early, so that the levels amplified on the bit lines have not yet been taken to saturation to a sufficient extent, then an only inadequately amplified signal is written back to the memory cells. The stored information is weakened as a result. In the event of a subsequent activation of such memory cells, it can happen that the stored information cannot be reestablished. On the other hand, if the turn-off of the word lines lasts too long, although there is certainty that the data signals have been amplified to a sufficiently high level, a subsequent memory access can only be effected when the word line is completely inactivated. The operating speed is reduced by a lengthy precharge operation. If the precharge operation starts too late, then precharge time is lost unnecessarily. A subsequent activation command in the same region of the memory cell array can lead, under certain circumstances, to an incorrect assessment of the cell information.
Particularly, in semiconductor memories operated clock-synchronously, so-called SDRAMs (Synchronous Dynamic Random Access Memories), the processing operations in the semiconductor memory are handled clock-synchronously, so that the precharge operation is initiated after a predetermined number of clock cycles after an activation of a memory cell. The coupling of a fixed delay time after an activation of the memory cell array for the initiation of the precharge operation has the disadvantage that the individual switching speeds of the functional elements of the semiconductor memory itself and of the entire system are not taken into account.
By way of example, a precharge operation can be initiated asynchronously after an activation of the memory cell array. For this purpose, a fixed delay time is generated on-chip for example by the charging of a capacitance. What is disadvantageous is that the exact setting of such a delay time is difficult on account of thexe2x80x94as is knownxe2x80x94not inconsiderable production-dictated variation of absolute parameters of integrated components. The delay time is temperature-dependent, moreover. The current consumption caused by the charging of capacitances is not inconsiderable, moreover.
Synchronous measures count the clock pulses of the externally applied clock signal and initiate the precharge operation after a predetermined number of clock cycles have elapsed after the activation of the memory cell array. What is disadvantageous here is that the operating frequency of the semiconductor memory must be complied with as exactly as possible. If the semiconductor memory is to be operated in a relatively large operating frequency range, then it can happen at a high operating frequency that the counted clock cycles have elapsed so rapidly that the amplifying operation of the sense amplifier is not yet sufficient before the precharge operation is initiated. At a low operating frequency, it can happen that there is an unnecessarily long wait before the required number of operating clock cycles has been counted. A renewed memory access is delayed ever further in an unnecessary manner here. Furthermore, it should be taken into account that clock-synchronous semiconductor memories can co-operate with memory controllers which alter the operating frequency considerably particularly in the standby mode. These conventional concepts therefore have the disadvantage that they can either only be realized in a complex manner or cannot be adapted flexibly enough to changing operating conditions.
It is accordingly an object of the invention to provide a semiconductor memory with precharge control, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and wherein the precharge operation is initiated at a point in time that is as optimal as possible after an access to the memory cell array, independently of the operating conditions that are currently present.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor memory, comprising:
a memory cell array having a multiplicity of word lines and a multiplicity of bit lines and having a multiplicity of memory cells connected to one of the word lines and one of the bit lines, the word lines having an active level, at which an access to memory cells is possible, and a nonactive or inactive level, at which an access to memory cells is not possible;
a control device in order to allocate the nonactive level to the word lines of the memory cell array;
a first and a second reference bit line, which are connected in a switchable manner to a respective terminal for a reference potential;
a comparison device, which, on the input side, is connected to at least one of the reference bit lines and, on the output side, generates a control signal depending on which the control device is caused to apply the nonactive level to the word lines.
The semiconductor memory according to the invention controls the waiting time until initiation of the precharge operation independently of the operating clock of the semiconductor memory or independently of a fixedly predetermined delay time. Rather, the precharge operation is initiated by monitoring the amplifying the operation at the pair of reference bit lines. If it is ascertained that sufficient amplification is present, the precharge operation is initiated. This point in time is chosen such that, or the one hand, the information is written back to the memory cell after having been amplified to a sufficient extent that it can be read out without any errors in the event of the next activation, and, on the other hand, initiation is nonetheless effected as early as possible in order not to lose any unnecessary waiting time. The externally supplied operating clock of the semiconductor memory is no longer important in defining the point in time of the precharge. Although additional outlay on circuitry is required, the additional area taken up in the semiconductor chip is compensated for by the gain in operational reliability.
It is important that the reference bit lines and the conditions present thereon correspond as exactly as possible to the conditions on a normal bit line pair ready for operation. Ideally, the worst-case conditions present on a normal bit line pair are simulated on the reference bit line pair. For this purpose, the reference bit line pair is expediently arranged at the edge of a memory cell array. The bit lines are connected to reference potentials via switching elements, which may be switching transistors. The reference potentials are slightly different from one another in order, compared with an information value stored in a memory cell, to generate a slight asymmetry on the reference bit line pair. This asymmetry is subsequently amplified and assessed in order to control the initiation of the precharge operation in a manner dependent thereon. One of the reference potentials expediently lies in the center of the settled signal levels of the bit lines for the complementary information signals to be stored, that is to say in the center of a bit line high level and a bit line low level. The other of the reference potentials preferably lies above that by a voltage offset xcex94U. The voltage offset xcex94U ideally corresponds to a stored data value which can be read from a memory cell. During the precharge operation, these reference levels are applied to the bit lines via the switching transistors. During the read-out operation, the reference levels are isolated from the bit lines, so that the amplifying process can be initiated.
In accordance with a preferred feature of the invention, only one of the reference bit lines is connected to an input of a comparison device. The comparison device may be embodied as a differential amplifier. That bit line to which the higher reference potential is applied is connected to the input of the comparison device. The other input of the comparison device is driven by the high bit line level. A switching signal is derived from the output of the comparison device and is transmitted to the superordinate control unit of the semiconductor memory. Said control unit thereupon initiates the precharge operation and generates the required control signals for the memory cell array. The control device is conventionally embodied as a state machine. In an advantageous refinement of the invention, a comparator is connected downstream of the comparison device. Another input of the comparator is controlled by a further reference potential. The comparator switches when the level on the reference bit line fed into the comparison device has risen to such an extent that the difference between this level and the high bit line level falls below a predetermined value. This predetermined value is formed by the ratio of the further reference potential to the gain factor of the differential amplifier. The switching signal which controls the state machine is present at the output of the comparator.
The provision of reference potentials which are to be applied switchably, i.e., selectively, to the reference bit lines has the advantage that the voltage offset xcex94U can be set exactly during a test of the semiconductor memory. For this purpose, a voltage generator is available which is provided with fusible links, so-called fuses or antifuses. The voltage generator has, for example, a resistor network wherein resistors can be connected in or disconnected by means of the fuses/antifuses. Test methods for semiconductor memories provide for supply voltages that are fed in to be varied and for the semiconductor memories thereupon to be tested for functionality under various operating voltages. In the case of the invention, with the inclusion of these voltage tests, it is possible to determine the optimum point in time for initiating the precharge operation. From this, the optimum value for the voltage offset xcex94U is determined and set by means of the fuses/antifuses.
The reference potentials are coupled in to the reference bit lines via respective transistor switches. The circuits are turned on during the precharge phase. If n-channel MOS transistors are used as switching transistors, these transistors are activated by the control signals which initiate the precharge operation.
In order to ensure an as far as possible ideal simulation of the conditions on the normal bit lines in the reference bit line pair, a number of developments are conceivable. A delay path is additionally connected downstream of the output of the comparison device or of the differential amplifier, which delay path effects an analogously asynchronously generated delay time. The delay time is a measure of the so-called write-back time. This time duration is necessary in order to write the signals amplified by the sense amplifiers of the normal bit lines back to the memory cells. By virtue of the fact that the differential amplifier is only connected to one of the reference bit lines, an asymmetrical capacitive loading of the reference bit lines may be present. The additional capacitive load caused by the input of the differential amplifier can be compensated for by an additional capacitance which is connected on the other reference bit line not connected to the differential amplifier. Finally, the reference bit line pair differs from the normal bit line pairs by virtue of the input capacitance of the differential amplifier and, if appropriate, by virtue of the additional compensating capacitance mentioned above. In order, from this standpoint, to make the conditions on the reference bit line pair equal to the conditions on the normal bit line pair, the reference bit line is dimensioned to be correspondingly shorter compared with the normal bit lines, in order to apply, in total, in each case identical capacitive loads to the sense amplifier.
It suffices in principle, to provide one reference bit line pair per memory bank. Other architectures of semiconductor memories provide even smaller organization units, so-called memory segments within a memory bank. In this case, it is possible to arrange one reference bit line pair per memory segment. A memory bank is in this case an inherently completely functional memory section which is addressed independently of another memory bank.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a Semiconductor Memory With Precharge Control, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.